A QDR (Quad Data Rate) SRAM device comprises two ports that operate independently at twice a rate of a conventional synchronous type memory and can transfer four data items per clock cycle (refer to reference 1 (non-patent document)). A data port of a QDR II, which is a QDR SRAM family product, is divided into an input port and an output fort and functions at a DDR (double data rate).
Reference 1 (Non-patent Document 1):
Nihon Cypress K. K., CYPRESS News Release, “NPF-LA-1 Interface Specification Compatible with QDR SRAM” [Searched on Oct. 3, 2002] Via Internet <URL: http://www.cypress-japan.co.jp/cynews020715.html>
As is well known, since a DRAM (dynamic random access memory) device requires a refresh operation and a pre-charge operation for a bit line, an SRAM device is excellent in terms of a data access cycle. On the other hand, in an SRAM device, each cell is constituted from four or six transistors. A high resistive load type cell is constituted from four transistors, i.e., two selection transistors connected to a pair of bit lines and two transistors with their gates and drains cross-connected to each other. A CMOS type cell is constituted from the six transistors. In a DRAM device, a cell is constituted from one transistor and one capacitor. It means that a DRAM is superior to an SRAM in an area, power dissipation, and a cost. Thus, there is proposed an enhanced bus turnaround DRAM which aims at improvements in device integration, power dissipation, and the cost as well as provides advantages of a conventional ZBT SRAM device having pin-outs, a timing and function sets similar to those of the SRAM. (refer to a reference 2 (patent document), for example).
Reference 2 (Patent Document 1):
JP Patent Kokai Publication JP-P2001-283587A (p. 2, FIG. 1)
A memory device described in the above reference 2 (Patent Document) includes a WAIT signal output pin for informing to a controller outside the memory device that a memory array is in a state which cannot be used for data access. The above reference 2 (Patent Document), there is such a description that its object is to provide an enhanced bus turnaround DRAM with pin-outs, timing, and function sets similar to those of the ZBT SRAM device and having a lot of same advantages as the ZBT SRAM device. However, the device described in the reference 2 is not ZBT-SRAM compatible. That is, in the above reference 2, use of a two-port DRAM cell is not described, and a usual one-port DRAM cell is considered to be used. There is a need to always insert a refresh cycle between read/write cycles; and in the refresh cycle, read/write operations must be interrupted. When the DRAM is used in a communication application, specifications for enabling continuous read/write operations are required. In such a communication application, the conventional ZBT SRAM cannot be replaced by the enhanced bus turnaround DRAM described in the reference 2. In a paragraph number [0059] in a detailed description of the above reference 2, it is described that when the refresh cycle is hidden behind a readout cycle of a cache, an effect of almost every refresh cycle on an operation of the memory device is minimum. However, even if a frequency of making read/write requests is low, when the read/write requests for the memory array about data not on the cache became continuous, the read/write operations had to be interrupted using the WAIT pin and hence the ZBT SRAM cannot be replaced by the enhanced bus turnaround DRAM.
On the other hand, as shown in FIG. 13, there is known a dynamic random access memory (refer to a reference 3 (Patent Document 2), for example). This memory includes a cell array with a plurality of memory cells, which are two-port DRAM cells. In each two-port memory cell, first and second switch transistors 205 and 206 are connected in series between a bit line 201 for normal access and a bit line 202 for refresh only. A capacitor element 207 for data storage is connected to a connection node at which the first and second switch transistors 205 and 206 are tied. A word line 204 for normal access and a word line 203 for refresh only are connected to respective control terminals of the first and second switch transistors 205 and 206. In this memory, when an external memory access and a refresh have been made to an identical address, the refresh is masked.
There is also known a memory (refer to a reference 4 (Patent Document 3), for example). In this memory, the two-port DRAM cells shown in FIG. 13 are employed; and write-only bit lines and read-only bit lines are provided, and a read and a write are simultaneously performed. For a refresh, cell data is read from a read-only bit line, and amplified by a sense amplifier. Then, the cell data is written back through a write-only bit line.
Reference 3 (Patent Document 2):
JP Patent Kokai Publication JP-A-3-263685 (p. 2, FIG. 2)
Reference 4 (Patent Document 3):
JP Patent No. 2653689 (p. 3, FIG. 2)